| Ibero-American Cooperation Network for Innovation in Sustainable Precision Agriculture with IoT Techniques |
2025-2028 |
This Ibero-American cooperation network will accelerate IoT for sustainable precision agriculture in Argentina, Bolivia, Peru, Uruguay, and Spain. The program builds capacity via workshops, open repositories, exchanges, and training in IoT sensing, flexible electronics, bio-impedance, energy harvesting, and open-source IC design. As a hands-on outcome, partners will co-develop, calibrate, and field-validate a low-cost, biodegradable wireless soil sensor measuring water potential, pH, nitrate, and temperature across diverse soils and climates. Custom power management targets multi-year life. Results will be disseminated through scientific venues and agrarian forums, advancing affordable, real-time crop monitoring and strengthening regional food-system resilience. |
| Semiconductors and Electronics HUB |
2025-2028 |
An Open Lab to equip startups, universities, and the electronics/semiconductor industry with tools to prototype products and develop talent. The hub centers on a CAD lab with licensed and open-source tools for IC and PCB design; it provides scheduled PCB and multi-project IC fabrication (twice yearly), a basic component stock, and targeted training. It links UCU’s existing IC characterization (Semic-Lab) and prototype assembly/test lab (Lab DeCe) into a single pipeline from design to assembly and measurement, accelerating R&D, reducing barriers to fabrication, and building a skilled workforce. |
| Optical Sensors and Systems for Real-Time Speckle Correlation |
2025-2027 |
This project will design, characterize, and control CMOS image sensors with interconnected pixels that compute speckle correlation directly in hardware. Under coherent illumination of rough surfaces, speckle fluctuations encode displacement and vibration. Our architecture continuously measures speckle shift, outputting an analog signal proportional to the real-time correlation between the incoming pattern and a stored reference. Unlike commercial cameras that capture frames and correlate digitally, our approach eliminates heavy processing, reducing latency and power. We will benchmark against ad-hoc correlating sensors and conventional cameras with external processing, demonstrating higher-bandwidth displacement/vibration sensing and enabling new real-time metrology applications. |
| Compact Noise and Mismatch Models for MOS Transistors in Proprietary and Open-Source Simulators |
2025-2027 |
This project will extend the ACM2 charge-based MOSFET model with physics-consistent noise and mismatch formulations. ACM2 compactly captures DC currents/charges and small-signal behavior across weak-to-strong inversion with just five DC parameters for bulk (plus one for SOI back-gate effects), and simple extraction. Adding noise and mismatch broadens its utility from pre-simulation to accurate predictive design. We will validate the new models via proprietary and open-source circuit simulators and on-silicon measurements using test chips (single transistors and low-noise amplifiers) fabricated in commercial processes and an open-source PDK. |
| Standardization and Optimization of Fresh Mushroom Cultivation: Validation of New Substrates and Development of By-Products |
2025-2026 |
La Esporada, a Uruguayan company with over 15 years of experience in mushroom cultivation, is expanding its production and developing new mushroom-based food products. Supported by Latitud and the Universidad Católica del Uruguay (UCU), the project focuses on automating key cultivation processes, testing alternative substrates, and creating an innovative mushroom-based protein product. The goal is to improve efficiency, reduce costs, and access new sustainable markets. |
| Smart Industrial Connectivity - Cámara de Industrias del Uruguay |
2024-2025 |
This project is a collaboration between the Cámara de Industrias del Uruguay (CIU) and the Department of Engineering at the Universidad Católica del Uruguay (UCU). Its main objective is to introduce Industry 4.0 technologies into seven industrial companies across Uruguay. The initiative aims to drive digital transformation in the local manufacturing sector by implementing advanced tools such as automation, data analytics, and smart production systems. Through this effort, the project seeks to enhance productivity, competitiveness, and innovation within the participating companies. |
| ISO 11784/5–Compliant Integrated Circuit for RFID Reading in the Agro-Industry |
2022-2025 |
This project will develop an application-specific integrated circuit (ASIC) in CMOS-HV technology with a low-frequency RFID reading engine compliant with ISO 11784/5. This standard applies to ear tags and implantable tags (transponders) for animal identification. It would be the first integrated circuit to implement this protocol in full—including both HDX and FDX options provided by the standard—which is necessary for commercial and/or certified readers. The project is supported by BQN Uruguay, a company with over 10 years of experience manufacturing RFID readers for animal traceability. |
| Characterization and Modeling of Very-Low-Frequency Noise in Gas Sensors |
2022-2025 |
Recent advances have produced gas-sensitive conductors (VOCs, CO, NH₃) enabling cheaper, lower-power gas sensors, but adoption is limited by aging and low-frequency noise. While sensitivity and selectivity are well studied, these two issues are not. This project will measure and model very-low-frequency noise in polyaniline, polypyrrole, and graphene, and assess aging via periodic I–V curves, step responses, and noise evolution. Using VOCSens samples in a temperature-controlled Faraday cage, we will build an autonomous, low-power system for long-term, high-resolution recordings and statistical analysis. Results will clarify limits of resistive gas sensors and guide improved designs. |
| Digital Logistics Solutions Demonstration Center |
2022-2025 |
Fundación Tecnolog will launch a Digital Logistics Solutions Demonstration Center with three pillars: (i) live demonstrations of IoT, electronics/robotics, software, data science, and blockchain; (ii) SME innovation training to reduce adoption barriers; and (iii) a professionalized Logistics Observatory building on a decade of UCU–RAS work. As a nonprofit consortium linking academia, industry, and chambers, Fundación Tecnolog promotes testing, research, and environmentally responsible innovation while fostering entrepreneurship and skills. The project targets >300 Uruguayan SMEs, accelerating uptake of logistics technologies to improve competitiveness and efficiency across the sector. |
| Bilateral Cooperation for Developing Decision-Making Models for the Agricultural Sector |
2022-2024 |
This project aims to accelerate technification in complex agricultural and livestock systems in Mexico and Uruguay, improving resource use among small- and medium-scale producers. The project will develop and validate process models, strengthen scientific and academic capacity through training and collaborative R&D, and disseminate open resources. Pilot deployments will demonstrate productivity and sustainability gains, generating scalable guidelines tailored to local contexts and incentivizing broader technology adoption across the sector. |
| Three-Level Flying Capacitor DC-DC Buck Converter for High-Efficiency Energy Power |
2022-2023 |
This project focused on the development of multi-phase Buck-type DC-DC converters intended for use in CubeSat-class satellites. The main emphasis was placed on leveraging open-source tools throughout the design and implementation process, promoting accessibility and innovation. |
| Application of Low-Power Techniques to Programmable Photodetector Circuits |
2021-2024 |
This project proposes to deepen the knowledge in the design and fabrication of photodetector integrated circuits based on interconnectable pixel arrays, aimed at pattern detection. The goal is to optimize the design to develop a device suitable for use in industrial environments and dedicated experiments. The aim is to achieve a low-power chip with greater noise tolerance, capable of operating in the field without performance loss. The new designs should be integrated into more advanced manufacturing processes that allow for a higher level of integration. |
| NEON - Network of competence on IoT |
2021-2024 |
NEON is an Erasmus+ Capacity Building project to accelerate IoT development in Argentina and Uruguay by strengthening and diversifying human-capacity training. We will create a cross-country Network of Competence linking universities and local companies to align needs, exchange know-how, and co-develop curricula. The network will support faculty and staff development, student training, internships, and joint university–industry laboratories, upgrading infrastructure and harmonizing offerings in state-of-the-art topics. By addressing current constraints—scarce specialized talent and fragmented education—NEON aims to produce industry-ready technicians and graduates, catalyze applied research, and broaden participation in IoT across academia and industry. |
| Design of Components and Integrated Circuits for Flexible Electronics |
2020-2024 |
This applied-research project evaluates the feasibility and performance of flexible electronics—printed transistors, diodes, and related devices produced by ink deposition—and their integration into complex systems combining ICs and sensors. We will characterize electrical/mechanical reliability, interconnects, and packaging, prototype circuits on flexible substrates, and benchmark against conventional implementations. The goal is to deliver design rules, demonstrators, and transfer-ready engineering solutions that leverage low-cost manufacturing to enable new applications. Outcomes will support Argentina’s economic and social development through scalable, high-value flexible-electronics technologies. |
| Pilot Line for Electronic Circuit Assembly |
2020-2021 |
This project establishes a basic pilot line for small-batch electronics manufacturing (tens to hundreds of units), enabling startups to iterate and commercialize early runs. The line will also deliver hands-on training for students, professionals, and entrepreneurs in PCB assembly. Equipment includes a manual solder-paste applicator, a pick-and-place robot, and a reflow oven—the minimal toolkit for surface-mount (SMD) production. By providing immediate series-manufacturing capability, the facility addresses a recurrent bottleneck that has hindered past projects, accelerating product validation, improving build quality, and de-risking the transition from prototype to market. |
| Extending the Linear Range of Amplifiers, Filters, and Other MOS-Transistor Circuits via Substrate Degeneration |
2019-2022 |
The project investigate MOS-circuit linearization via bulk (substrate) modulation to reduce distortion in amplifiers, filters, and related blocks. The project combines theory, simulation, and silicon measurements of custom ICs, covering all operating regions (linear/triode/saturation; weak/moderate/strong inversion). We will devise new structures that exploit the substrate to minimize THD/HD3 while analyzing trade-offs with noise and offset. Demonstrator amplifiers and filters will validate gains in practical conditions. Emphasis is on ultra-low-power designs for implantable medical devices, with broader relevance to RF/telecom, audio, and sensor interfaces. |
| Impact of New Application Technologies for Biological and Conventional Pesticides on Fruit and Vegetable Safety and Environmental Contamination |
2018-2022 |
This project will optimize pesticide application to improve produce safety, worker health, and environmental protection in two systems: greenhouse vegetables (NW) and deciduous fruit/vineyards (South). For orchards, we will compare application technologies for pest-control efficacy and emission reduction, quantify drift to derive multi-organism risk indicators, and develop smart sprayers to cut pesticide use. In greenhouses, we will adapt nebulization for conventional/biological products and refine hydraulic delivery of biopesticides. Residue analyses will assess fruit safety; worker exposure will be monitored. The consortium is formed by INIA, FING, FAGRO and UCU. |
| RISC-HV: High-Voltage RISC-V Processor for Medical Applications |
2018-2021 |
This project will design, fabricate, and characterize a high-voltage (HV) SoC integrating an ultra-low-power RISC-V CPU tailored for implantable medical devices. The chip adds programmable HV digital I/O, on-chip voltage boosters, and a current-mode stimulator, enabling mixed-signal therapy/monitoring in a single die. Reliability and patient-safety requirements (isolation, ESD/LU, fault detection) will be verified to comply with medical-device standards. Silicon prototypes will quantify energy, stimulation accuracy, and HV drive capability. The project delivers the first HV RISC-V SoC optimized for micro-power implants, reducing size and power while simplifying system design. |
| Living Museums: Technology for Cultural Inclusion |
2016-2018 |
This projects aims to co-create inclusive, technology-enabled museum experiences. Building on contemporary museology and digital engagement, the project designs accessible IoT and multimedia tools that enhance bidirectional communication and attract new audiences. Responding to national and international rights frameworks and persistent physical, informational, communicational, and attitudinal barriers, we will prototype solutions that improve access to cultural content—especially for people with sensory disabilities. Outcomes include tested accessibility interventions, staff training, and practical guidelines to inform sustained inclusion policies and scalable adoption across museums. |
| Emprender |
2015-2024 |
An outreach program with Fundación Telefónica re-engaging youth who have left or risk leaving school. We deliver foundational training in programming, electronics, and IoT through hands-on workshops and project-based learning, paired with mentoring and employability skills (communication, teamwork, CVs, interviews). |
| Cyclostationary Flicker Noise in MOS Transistors |
2013-2015 |
Flicker (1/f) noise from random charge trapping in MOS oxides limits RF links, amplifiers, sensors, and memories. Interest is growing in cyclostationary flicker noise (RFC) under periodic biasing, which can reduce device noise, yet a simple analytical PSD that fully explains measurements is lacking. We will combine numerical simulations with experiments on a custom IC integrating diverse test transistors and low-flicker amplifiers to measure RFC across bias regions. We will fit and interpret the data using existing models and physics-based hypotheses. Goal: a clearer picture of RFC and its PSD, including reemergent 1/f at low frequencies. |
| Micromanipulator and High-Frequency Oscilloscope |
2013-2014 |
This project will equip UCU’s microelectronics lab with a precision micromanipulator and a 4 GHz mixed-signal oscilloscope—unique in Uruguay—to establish an open IC-characterization facility. The micromanipulator enables micron-scale probing of bare dies; the oscilloscope supports high-bandwidth analog/digital analysis. The lab will multiply the volume and quality of measurements, accelerating research, innovation, and technology transfer. It will serve academic groups in micro/nanoelectronics, applied electronics, and embedded systems, as well as companies prototyping communication and medical-electronics devices. |
| MERCOSUR Joint Research Projects Program (MRC_C_2011_1_15) |
2011-2013 |
This project will strengthen the microelectronics partnership between Universidad Nacional del Sur (Argentina) and Universidad Católica del Uruguay. Technically, the program pursues two goals: (1) train human resources in microelectronic design through joint courses, co-advised theses, and exchanges; and (2) develop reconfigurable analog and mixed-signal circuits for diverse applications with power consumption superior to the state of the art. Research will produce innovative low-power techniques and validated demonstrators, yielding publishable results and reusable IP. Outcomes include a sustainable binational collaboration, a skilled talent pipeline, and energy-efficient circuit blocks ready for transfer. |
| Integrated Circuits for Implantable Medical Devices |
2011-2012 |
Implantable medical devices demand ultra-low-power ICs and robust voltage references insensitive to battery droop. We will design, fabricate, and characterize an integrated, micro-power voltage reference suitable for active implants, validating performance under medical safety constraints. We will also compare active versus conventional current mirrors in such circuits, quantifying benefits and penalties. In particular, we will investigate architectures that boost common-mode rejection (CMRR) without substantial power overhead, accepting area trade-offs when justified. Outcomes include a validated reference and design guidelines for low-power analog blocks in battery-operated implants. |
| Cardiac-Sensing Integrated Circuit |
2010-2012 |
This project will design a fully integrated cardiac-sensing front end in HV-CMOS for implantable devices, minimizing power while meeting safety requirements. Phase 1 delivers a low-noise amplifier optimized under HV constraints. Phase 2 adds switched-capacitor filter–amplifier stages as the second gain stage, with techniques to limit charge injection and power. A low-power, ultra-low-offset comparator completes the readout chain. The system targets micro-watt operation and robust patient safety, enabling accurate, long-term cardiac monitoring. |
| Analytical Modeling and Electrical Characterization of Multi-Gate SOI-MOS Transistors with Uniformly Doped and Graded Channels |
2009-2011 |
This project studies and models key variables governing analog use of graded-channel and multi-gate SOI transistors. Using electrical characterization and 2D/3D device simulations, we will quantify low-frequency and thermal noise, generation–recombination lifetimes, and related parameters across bias and geometry. Physics-based compact models will be extracted and validated against measurements, enabling accurate circuit-level prediction of noise and dynamic behavior. Outcomes include guidelines for low-noise analog design and parameter sets tailored to SOI technologies. |
| Low-Noise Integrated Amplifiers: Design and Characterization |
2009-2010 |
Noise limits analog IC performance, especially in implantable medical devices constrained to microwatts. This project designs and characterizes ultra-low-noise, micro-watt integrated amplifiers targeting EEG. We advance chopper architectures using switched transconductors and aggressive supply-voltage reduction, extending our prior work (“On the reduction of thermal and flicker noise in ENG signal recording amplifiers,” Springer) from milli-watt ENG amplifiers to micro-watt EEG front ends. Prototypes will be fabricated in HV CMOS commonly used for implants to ease translation. The effort includes establishing a dedicated low-frequency noise laboratory to enable precise measurements and accelerate technology transfer. |
| Integrated Switches for Implantable Medical Devices in HV-CMOS Technology |
2008-2010 |
Implantable medical devices require reliable control of tissue stimulation. We designed, fabricated, and characterized three integrated high-voltage switches that pass or block voltage (0.1–16 V) and current (100 µA–30 mA) stimuli for multiple therapies. Devices achieve less than 5 Ω on-resistance at 2–5 V supply, less than 1 µs turn-on/off, bidirectional operation, low crosstalk, ESD protection, and single-fault safety (no DC delivery or few µA under gate failure). Implemented in trench-isolated HV CMOS, the switches meet broad implant requirements and enable compact, safe stimulators. |
| Mismatch Modeling in MOS Transistors and Applications |
2005-2007 |
This project address MOS transistor mismatch, a key source of offset limiting modern analog/digital ICs as device dimensions shrink and supply voltages fall. The project will (i) review state-of-the-art mismatch models and offset-reduction techniques; (ii) develop a simple, physics-consistent mismatch model for nanometer CMOS; (iii) validate it via simulation and silicon measurements; and (iv) propose offset-reduction circuit architectures, including series–parallel transistor associations where the model confers advantages. We will design, fabricate, and test an IC with dedicated structures to quantify offset, providing practical guidelines for robust, low-voltage analog design. |
